1. Field of the Present Invention
The present invention generally relates to the field of power systems and more particularly to voltage converters for use in computer systems and related technologies.
2. History of Related Art
The simplicity and effectiveness of synchronous converters makes them a popular choice in the design of non-isolated DC to DC voltage converters. The utility of a conventional synchronous converter is limited in a wide variety of applications by constraints on the gain achievable with such circuits (where gain refers to the ratio of the converter's output voltage to input voltage). More specifically, it is desirable in numerous applications to convert a relatively high voltage DC signal to a relatively low DC output signal. The high voltage DC signal is useful for distributing power to various components of a system with a minimum of distribution loss. The high voltage signal is typically not, however, preferred at the load point for many applications and thus it is frequently necessary to implement a DC voltage converter with a gain significantly less than one (i.e., a converter capable of producing a low voltage output from a high voltage input). Most notably in computer system applications, the desired load point voltage has decreased in recent years while the power and current requirements has increased, especially in high performance computer systems commonly referred to in the industry as enterprise systems. Enterprise systems are typically characterized by multiple high speed processors, high performance I/O and memory cards, and correspondingly, extremely high current and power requirements. The power demands of such systems place heightened significance on methods and circuits that are able to minimize distribution losses. Historically, it is known that distribution of DC power at the highest possible voltage is desirable to minimize I.sup.2 R power dissipation where R refers to the impedance of the distribution medium. In contrast to the demand for high distribution voltages, the trend in the supply voltages required for sub-micron semiconductor technologies used in state of the art computer systems is towards increasingly lower voltages. Where 12V and 5V supplies were once employed, 3.3V and 1.8V supplies are now implemented to combat well documented sub-micron effects of semiconductor transistors. The simultaneous desire for increasingly greater distribution voltages and increasingly lower load point voltages create a demand for DC to DC converters with gains significantly less than unity. Moreover, because these converters are typically packaged in close proximity to system electronics and because of the ever present demand to minimize the system package, it is highly desirable to implement the converter in the smallest and most cost effective manner available. Conventional synchronous converters offered these benefits for systems in which the gain required of the converter was not too demanding. For state of the art enterprise systems, however, conventionally designed synchronous converters typically cannot perform adequately because of fundamental limitations in the duty cycle associated with the pulse width modulation scheme utilized in synchronous designs. In conventional synchronous converters, the gain is proportional to the duty cycle of the pulse signal used to drive the converter. Unfortunately, practical limitations on the lower limits of achievable duty cycles limit the performance (i.e., the gain) of the converters. Due to the presence of inevitable stray capacitance, the pulse signal produced by any system will require finite rise and fall times that place fundamental limits on the duty cycles achievable. These limitations impose a significant constraint on the ability of system designers and manufacturers to minimize power dissipation in high performance computer systems through the use of a high voltage distribution system. Therefore it would be highly desirable to implement a converter incorporating the benefits of conventional synchronous designs while simultaneously enabling significantly wider latitude in the output voltage to input voltage ratio. Moreover, it would be desirable to implement such a design with at a minimum cost, complexity, and dimension, in a design compatible for use in close proximity to high speed, low voltage digital circuitry without diminishing the system reliability or performance.